This invention relates to memory devices and particularly to non-volatile memory arrays and array architectures.
Array architectures are critical for memory devices. Array architectures play a key role in determining the efficiency, power consumption, read/write speed, reliability and other attributes of memory devices.
Nonvolatile memories are formed by arrays of memory cells where each memory cell typically has four terminals and a body. Each cell includes a control gate accessed through a word line and includes a source, a drain and a channel there between. The source and the drain are accessed through bit lines. Each cell may include a tunneling gate accessed through a tunneling line. Each cell includes a charge storage region for storing charges where the charge storage region is typically a floating gate. A body terminal is typically in a substrate and is common to all the cells on the substrate.
Nonvolatile memories generally need improved speed of operation, greater reliability, greater flexibility in the functional operation and smaller sizes for increased storage capacities.
In consideration of the above background, there is a need for improved nonvolatile memory devices and architectures for nonvolatile memories.